In order to reduce the footprint and improve the speed of integrated circuits various three-dimensional integrated circuit structures have been proposed. Traditional integrated circuit structures have been two dimensional, in that all the active devices have been formed in a same plane in a same semiconductor layer. Three-dimensional integrated circuits utilize vertically stacked semiconductor layers with active devices formed in each of the stacked semiconductor layers.
The fabrication of three-dimensional integrated circuits poses many challenges particularly in the methodology for interconnecting devices in the different semiconductor layers together. The total depth of these interconnects can exceed 1.5 um with diameters in the sub 0.2 um range. It is difficult to fill vias having such large depth to width aspect ratios with high quality, defect free metal. In particular, the metal fill of large aspect ratio and very deep vias often contain voids which can increase the resistance of the via and result in yield loss as well as reduce the reliability of the device. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.